In current complementary metal oxide semiconductor (CMOS) technology, a polysilicon gate is typically employed. One disadvantage of utilizing polysilicon gates is that at inversion the polysilicon gates generally experience depletion of carriers in the area of the polysilicon gate that is adjacent to the gate dielectric. This depletion of carriers is referred to in the art as the polysilicon depletion effect. The depletion effect reduces the effective gate capacitance of the CMOS device. Ideally, it is desirable that the gate capacitance of the CMOS device be high since high gate capacitance typically equates to more charge being accumulated in the inversion layer. As more charge is accumulated in the channel, the source/drain current becomes higher when the transistor is biased.
CMOS devices including a gate stack comprising a bottom polysilicon portion and a top silicide portion are also known. The layer of silicide in such a gate stack contributes to a decrease in the resistance of the gate. The decrease in resistance causes a decrease in the time propagation delay RC of the gate. Although a silicide top gate region may help decrease the resistance of the transistor, charge is still depleted in the vicinity of the interface formed between the bottom polysilicon gate and gate dielectric, thereby causing a smaller effective gate capacitance.
Another type of CMOS device that is available is one where the gate electrode includes at least a metal layer beneath a Si-containing, e.g., polysilicon, gate electrode. In such CMOS devices, the metal of the gate prevents depletion of charge through the gate. This prevents the decrease in effective thickness of the gate capacitance. Although metal-gated devices address the depletion problem mentioned above in regard to polysilicon gates, it is difficult to obtain nFET and pFET workfunctions using metal-gated devices due to instability in threshold voltage. This is especially the case when high k dielectrics such as Hf-based dielectrics are used as the gate dielectric of metal-gated devices.
In view of the above, and in order to continue the CMOS scaling trend using metal gate stacks, there is a need to provide a CMOS structure in which at least one of the metal gate stacks has an nFET workfunction and at least one other metal gate has a pFET workfunction. It is noted that the term “workfunction” as used herein refers to the effective workfunction of the dielectric stack and the gate electrode.